Much of the progress in the field of IC technology is associated with CMOS devices. CMOS devices combine NMOS and PMOS (n-channel metal-oxide semiconductors and p-channel metal-oxide semiconductors) transistors to achieve low power consumption and high device densities. These and other beneficial properties associated with CMOS devices have made them the preferred technology in many aspects of integrated circuit design. CMOS designs have, however, been susceptible to two common problems, latch-up caused by parasitic bipolar transistor effects and damage due to electrostatic discharge.
With respect to the latch-up problem, all MOS transistor ICs have pn junctions which can form parasitic bipolar transistors, where the substrate serves as the base, the drain serves as the collector, and the source serves as the emitter. Bipolar transistor action is particularly troublesome in CMOS circuits where the unwanted formation of cross-connected npn and pnp transistors is possible. Above a critical voltage level, a latch-up condition occurs and both bipolar transistors become unwanted amplifiers, causing quickly rising current levels through the transistors. During latch-up, control of the transistors is lost as the amount of current which passes through the MOS transistors is no longer a function of the gate voltage. Furthermore, damage may occur to the MOS transistors if the latch-up current flow is excessive or prolonged.
One way of preventing latch-up is to provide a low-resistance layer below the transistors. Typically the low-resistance layer is achieved by a buried layer implant. Since the substrate below the NMOS and PMOS transistors serves as the base region of the parasitic bipolar transistors, providing a low-resistance substrate makes it difficult to establish a sufficient voltage at the base (substrate) to forward-bias the pn junction between the base (substrate) and the emitter (source). The low resistance decouples the bipolar transistors, decreases the possibility of latch-up, and allows the NMOS and PMOS transistors to function as intended.
A low-resistance epitaxial layer in the substrate of a CMOS will also decouple the parasitic bipolar transistors and thereby improve latch-up performance, in much the same manner as an implanted low-resistance layer. However, the price of epitaxial layer substrates may be prohibitive. A more cost-effective alternative to obtaining similar benefits is to incorporate the low-resistance buried layer implant beneath the CMOS transistors in a bulk silicon substrate.
The second common CMOS problem relates to the high voltages which are present in the device during an ESD event. The pn junctions of the CMOS structure are subject to a number of voltage limitations including avalanche breakdown and punch-through. Punch-through refers to the condition where the drain voltage is increased to the point that the depletion region surrounding the drain region extends to and forward biases the source. The drain current then rises rapidly. Punch-through is generally not destructive, but control over the transistor operating characteristics is no longer possible during punch-through.
Breakdown voltages occur typically when the gate-to-source voltage reaches about 50 volts. At this high voltage level, the gate oxide is destroyed, causing permanent damage to the transistor. While the voltage required to cause breakdown is relatively high, MOS transistors have very high impedance and thus small amounts of static charge accumulated at the gate can cause breakdown voltage conditions to be exceeded. To prevent this type of damage, an ESD protection device is often used to clamp the voltage at the input of the CMOS device to a non-destructive level and to shunt the charge created during the ESD event to ground and away from the other components of the CMOS device.
A common technique of providing ESD protection in CMOS circuits involves utilizing the generally undesirable parasitic bipolar transistor action discussed above to form an ESD protection device. The ESD protection device uses one or more NMOS transistors as bipolar npn transistors with the drain functioning as the collector, the substrate functioning as the base, and the grounded source functioning as the emitter. During ESD conditions, sufficient voltage is developed at the collector (drain) and subsequently at the base (substrate) to forward bias the base and turn on the parasitic bipolar transistors. Current begins to flow through the bipolar transistors and the voltage at the collector (drain) quickly drops and is clamped at a level known as the snapback holding voltage. The collector (drain) is held at the snapback holding voltage and the current associated with the ESD is shunted to ground. The parasitic bipolar transistor continues in a conductive state until the current flow and associated voltage at the base are no longer sufficient to forward bias the base. Ideally, the parasitic bipolar transistors of the ESD protection device should "turn on" quickly and the collector (drain) voltage should be clamped at a level below the transistor breakdown voltage.
One method of increasing the effectiveness of the ESD protection circuit involves increasing the resistance of the substrate below the NMOS transistor. Increased resistance in the substrate allows easier turn-on of the parasitic bipolar transistor action which causes the ESD protection. Ideally, it is desired to have all of the current flow associated with the ESD event discharge through the protection circuit to ground. The disadvantage of a high resistance substrate is that it promotes the occurrence of the latch-up problem described above.
It is often desirable to implement both latch-up immunity and ESD protection in a CMOS device. However, while epitaxial substrates and low resistance buried layer implants serve to decouple the parasitic bipolar transistors, thereby improving latch-up performance in the CMOS device as a whole, they also degrade the ability to use the parasitic bipolar transistors for ESD protection.
It is with respect to this and other background information that the present invention has evolved.